SUMMARY
Wafer yield is a key indicator to pursuing excellence in semiconductor manufacturing. With the increased wafer size, the enhanced complexity and precision of wafer fabrication is possible. Using monitoring to improve the process by predicting the yield has become an important quality issue. Most research uses the number of wafer defects, the area of the wafer, and fixed statistical distribution to predict the yield. Such methods fail to establish a high yield model due to the random and system-wide distribution of wafer defects. This study proposes the Mahalanobis-Taguchi system (MTS) to determine the key variables from the wafer acceptance test (WAT), and establish a classification model of yield grade. The general regression neural network (GRNN) was used to build a predicted model of the wafer probe yield from selected common variables. A real case from a Taiwan manufacturer of dynamic random-access memory (DRAM) is used as an example. It can get the 82 key and significant sequence variables of the WAT, with classification precision of over 90% and the R2 of the GRNN prediction model at 0.73. Through demonstration, the result can effectively increase the yield and reduce the quality cost in DRAM manufacturing.